module charge
(
input clk,rst_n,
input avs_wr_n,
input [31:0]avs_writedate,
input  avs_address,
output reg[3:0]flag1
);
reg flag1_wr_n;
always@(avs_address)  begin
  flag1_wr_n<=1;
  case(avs_address)
   1'b1:flag1_wr_n<=1'b0;
	default:flag1_wr_n<=1'b1;
  endcase
end
always@(posedge clk)  begin
 if(!rst_n)
  flag1<=4'd0;
 else 
  if((!avs_wr_n)&&(!flag1_wr_n))
   flag1<=avs_writedate[3:0];
end

endmodule
